Scatterometry is used to estimate dimensions of fabricated structures, such as trench depth, trench sidewall angle, height of step of shallow trench isolation oxide above silicon surface. Typical scatterometry methods utilize a rectangular array having closely-spaced (e.g., nested), alternating lines and trenches in a grid. Results of such a scatterometry are highly applicable to SRAMs. However, such scatterometry methods neglect isolated structures, for instance, found in logic areas of fabricated semiconductor devices. Moreover, some characteristics of such isolated structures may not be extrapolated from measurements of nested structures. Accordingly, such results may be inapplicable to logic areas.
A need therefore exists for methodology and an apparatus for enabling scatterometry to be used to estimate dimensions for both SRAM and logic areas of fabricated semiconductor devices.